Zarlink Enables Carrier-Class Performance with New Digital Timing Chips for Networking Growth Markets

The ZL(TM)30102 and ZL30105 products target exciting high-growth networking equipment markets, including DSLAMs (digital subscriber line access multiplexers), wireless base stations, VoIP routers and gateways, as well as add/drop multiplexers, cross-connects, and PBXs. According to market research firm In-Stat/MDR, the DSLAM market alone will grow from approximately 60 million units shipped in 2004 to almost 100 million units in 2006.

"Our new DPLLs help customers deliver carrier-class services- availability, performance, and system maintainability in a wide range of SDH (Synchronous Digital Hierarchy), PDH (Pleisiochronous Digital Hierarchy), and datacom applications," said Andy Turudic, product line marketing manager, Network Communications, Zarlink Semiconductor. "Using proprietary spectrum- shaping and clock-generation algorithms, these DPLLs are well positioned for new design-ins and to take market share with competitive pricing, industry- leading jitter performance, and value-added features such as redundant, Stratum 3/4/4E compliant clocks, and frame-pulses."

Support for TDM switching

The ZL30102 and ZL30105 chips also generate ST-BUS, supporting Zarlink's full line of TDM (Time Division Multiplexing) switching solutions, and other TDM clock and framing signals that are phase aligned to one of three network references or to another system primary-clock reference. The chips accept three input references and synchronize to 2 KHz, 8 KHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs. They deliver significant improvements in lock time, support manual or automatic reference switching, and have excellent holdover accuracy - all key elements in timing performance. Both devices are managed through a simple hardware control interface.

Superior system reliability

With networks trending toward higher speed, IP-based equipment, implementing advanced timing and synchronization is more challenging. Designers striving to improve system reliability are demanding redundant timing control and monitoring to ensure continued operation during network upgrades or disruptions. Zarlink's new DPLLs provide constant monitoring of the clocks and maintain close phase alignment between a "primary" and "secondary" clock under network, or intra-system, jitter and wander conditions - allowing hitless, manual or automatic switching to a working secondary clock if the primary clock begins to exhibit failure.

Fully featured T1/E1 DPLL

The ZL30102 device builds on the ZL30100 DPLL, released earlier this year, and is the most comprehensive T1/E1 terminal equipment DPLL on the market. The ZL30102 timing chip meets Stratum 4/4E clock requirements and is applicable to H.110 and similar proprietary systems. The chip's outputs also generate the industry's lowest jitter - below 0.6 ns (nanoseconds) peak-to- peak, with jitter filtering from 1.8 Hz.

Comprehensive set of SDH and PDH clock frequencies

The ZL30105 chip is a simple-to-use Stratum 3/4/4E SDH DPLL and includes ITU-T (International Telecommunications Union-Telecommunications) G.813 option 1 compliance, reference clock monitoring, and automatic or manual hitless reference clock selection features.

Utilizing proprietary clock-generation techniques, the device simultaneously generates four harmonically unrelated families of reference- locked SDH and PDH clocks - 1.544 MHz, 2.048 MHz, 19.44 MHz and DS2/E2/DS3/E3 - for flexible timing card applications. In competing PLLs, a harmonic relationship is generally needed to produce locked clock outputs, precluding them from producing numerous clocks.

Optimized for Advanced TCA

The ZL30105 chip also directly provides low-jitter clock and frame-pulse support for the emerging Advanced TCA bus. This bus is expected to proliferate across telecom and datacom equipment, analogous to the use of PCI cards as building blocks in today's computer and test systems. The proprietary jitter shaping, cleanup, and filtering techniques in the ZL30105 DPLL - resulting in 600 ps (picoseconds) of worst-case unfiltered peak-to-peak jitter and exceeding stringent OC-3 jitter requirements - enables its use in tandem with a Zarlink frequency multiplying analog PLL to produce even higher line rate clocks, with low combined jitter, than those supported by the device's 19.44 MHz output.

Applicable standards

Zarlink's DPLLs meet the requirements of Telcordia GR-1244-CORE for Stratum 3/4/4E, ITU-T G.823, G.824, and G.813 option 1, and ANSI (American National Standards Institute) T1.403.

Availability, packaging and price

The ZL30102 and ZL30105 DPLLs are in volume production. The chips are offered in a 64-pin TQFP (thin quad flat pack) measuring 10x10 mm (millimeters). In 1K quantities, the ZL30102 device is priced at US$22.50 and the ZL30105 chip at US$27.50. For more information, please visit: http://products.zarlink.com/product_profiles/ZL30102.

About Zarlink Semiconductor

For almost 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The Company's success is built on its technology strengths, including voice and data networks, consumer and ultra low-power communications, and high-performance analog. For more information, visit http://www.zarlink.com/.

Certain statements in this press release constitute forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Such forward-looking statements involve known and unknown risks, uncertainties, and other factors which may cause the actual results, performance or achievements of the Company to be materially different from any future results, performance, or achievements expressed or implied by such forward-looking statements. Such risks, uncertainties and assumptions include, among others, the risks discussed in documents filed by the Company with the Securities and Exchange Commission. Investors are encouraged to consider the risks detailed in those filings.

Zarlink, ZL, and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Advanced TCA is the trademark of PCI Industrial Computer Manufacturers Group.

CONTACT: Zarlink, Michael Salter, Media Relations,
613 270-7115, michael.salter@zarlink.com; United States, Natalie Sauve,
High Road Communications, 613 236-0909, nsauve@highroad.com; Europe, Simon
Krelle, Pinnacle Marketing Communications, 44 1908 2355 22,
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